1. Field of the Invention
The present invention relates to foaming vias in semiconductor substrates and the resulting via structures. More particularly, the present invention relates to methods for forming vias in semiconductor substrates such that active surface devices are not damaged during formation of vias through a semiconductor substrate.
2. State of the Art
Semiconductor devices including integrated circuitry, such as memory dice, are mass produced by fabricating hundreds or even thousands of identical circuit patterns on a single semiconductor wafer or other bulk semiconductor substrate using photolithography in combination with various other processes. It is a continual goal of semiconductor manufacturers to increase the density of semiconductor devices fabricated on a given size of semiconductor substrate to achieve increased yield of semiconductor devices and enhanced performance thereof. In recent years, efforts to increase the density of semiconductor devices in a semiconductor assembly have also intensified.
One method for increasing the density of semiconductor devices in a semiconductor assembly is to stack semiconductor dice to create a three-dimensional multichip module (3-D MCM). The formation of a 3-D MCM typically requires creating vias (i.e., through holes) in at least one semiconductor die that extend from its active surface to the opposing back surface thereof. The vias are filled with an electrically conductive material that electrically connects the via to the integrated circuitry fabricated on the active surface. Thus, the vias provide an electrical pathway from the active surface of a semiconductor die to its respective back surface, enabling interconnection of the back surface of the semiconductor die to external electrical contacts of another semiconductor die or a carrier substrate of the 3-D MCM.
Various methods for forming vias in semiconductor substrates have been disclosed. Etching and laser ablation or drilling are two frequently used methods. Etching employing photolithographic processing of a resist followed by wet (chemical) or dry (reactive ion) etching to define the vias may suffer from problems with precisely aligning the vias with the electrical components on the opposing surface of the semiconductor substrate and, particularly with wet etch chemistry, undercutting of substrate material below the photomask. Laser drilling has been used to form vias by ablating semiconductor material to form through holes extending through the entire thickness of a semiconductor die. Representative patents disclosing laser drilling vias are U.S. Pat. No. 6,667,551 to Hanaoka et al., U.S. Pat. No. 6,114,240 to Akram et al., and U.S. Pat. No. 4,445,978 to Whartenby et al. While forming vias using laser drilling has the advantage of being significantly faster and in some instances, more locationally accurate and dimensionally precise than forming vias by wet or dry etching, the laser drilling process may cause damage to the integrated circuitry of the semiconductor dice fabricated on the active surface of semiconductor substrate. This is, in part, due to the thermal input of the laser creating a three-dimensional (3-D) heat flow surrounding the heat affected zone (HAZ) in the substrate near the via being created. This 3-D heat flow can raise the temperature of the integrated circuitry forming the semiconductor devices proximate the via being drilled, causing degradation or malfunctioning of the semiconductor devices contained within the active region of the semiconductor die.
Accordingly, there is a need for a method of forming vias in semiconductor substrates by employing the ability to rapidly form precisely located and dimensioned vias offered by laser drilling without damaging the active surface devices during the laser drilling process.